FIFO memory systems are used in a wide variety of applications, such as buffering high-speed serial data immediately after it has been parallelized, for temporary storage of a data packet during packet processing, or buffering data going to or coming from a disk. Data values that are sequentially written to a FIFO buffer are read from the FIFO buffer in the same order, namely the first data entered into the FIFO memory system is the first data read from the FIFO memory system.
FIFO buffers are implemented in RAM and the flow of data into and out of RAM is controlled by address counters that track the read and write addresses being used. The address counters coordinate the data flow into and out of RAM to insure that memory is available to accept incoming data to prevent overflowing the RAM, and that data is stored in RAM before a read operation executes.
Several status flags are available in FIFO memory systems, such as FIFO FULL and FIFO EMPTY, which indicates the RAM is either full or empty, which indicate that there is sufficient space in RAM for a WRITE to occur or sufficient data in RAM for a READ to be performed. For example, if a WRITE function is to be enabled, the FIFO FULL status flag will indicate whether the data can be written into memory. If a read is to be performed, the FIFO EMPTY status flag will indicate whether there is any data available in the FIFO.
FIFO memory systems can be synchronous or asynchronous. A FIFO memory system in which both the read address counter and the write address counter are clocked by the same clock signal is referred to as a synchronous FIFO memory system. In contrast, a FIFO memory system in which the read address counter and the write address counter are clocked by different clock signals is referred to as an asynchronous FIFO memory system. Asynchronous FIFO memory systems are extremely useful in digital data systems where different sides of the FIFO memory system are independently clocked, either at different clock rates, or at the same clock rate, but with a phase difference (“skew”).
In both synchronous and asynchronous FIFO systems, the read and write address counters are circular counters that wrap around to an initial address after the last address is accessed. The read and write address counter output signals are either multiplexed to address a single-port random access memory (RAM), or they are separately provided to address different input ports of a multi-port RAM (e.g. a dual-port RAM).
FIFO memory systems have been implemented in PLDs using the fabric of the PLD to provide the control logic, generate the status flags, and provide the write and read addresses of FIFO memory systems. Such FIFO memory systems are described in co-owned U.S. Pat. Nos. 5,898,893 and 6,434,642, the disclosures of which are hereby incorporated in their entirety for all purposes. The logic for operating the FIFO memory system is typically developed in configurable logic blocks (“CLBs”) surrounding an embedded block of RAM (embedded “BRAM”), and the embedded BRAM or distributed memory is operated as a FIFO buffer.
It is often desirable to provide many FIFO memory systems in a single PLD, such as for use in digital networking systems that have many clock domains. This consumes both memory and CLBs, limiting their availability for other applications. FIFO memory systems often require buffers that are inefficient to implement in distributed memory, but use only a fraction of a dedicated BRAM, which unnecessarily consumes PLD resources. If a user requires many FIFO memory systems on a single PLD, much of the device's embedded BRAM resources may be allocated as FIFO buffers but not fully utilized. In some instances, the number of BRAM ports in a PLD, rather than the number of CLBs, may become the limiting factor.
Therefore it is desirable to provide a PLD with more efficient use of device resources, and to provide more FIFO memory systems on a PLD.